1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which a control signal is used to control an internal operation of the semiconductor memory device, and a control signal generating method thereof.
2. Description of the Related Art
A conventional semiconductor memory device comprises a control signal setting portion. The control signal setting portion sets a control signal responsive to a code signal applied from an external portion. The control signal setting portion receives a code signal applied from an external portion during a mode setting operation and decodes the code signal to set a control signal. The semiconductor memory device varies a delay time or an internal voltage of internal circuits responsive to the control signal. If the internal circuits of the semiconductor device do not operate normally, the semiconductor device can operate normally by setting the control signal to vary the delay time or the internal voltage of the internal circuits.
The conventional semiconductor memory device performs an AC characteristic test and a function test during a test operation. The AC characteristic test is to test a dynamic characteristic such as a signal delay time and an access time, and the function test is to test whether memory cells of a memory cell array of the semiconductor memory device are normal cell or defective cells by writing/reading data to/from the semiconductor memory device. The AC characteristic test and the function test are simultaneously performed. For example, it is tested whether an access time according to a specification (e.g., a time of from when a row address strobe signal RASB is activated until effective output data are outputted to an output terminal of the semiconductor memory device) is satisfied or not by performing the function test of the semiconductor memory device at a varied external power voltage while varying a level of the external power voltage.
FIG. 1A is a graph illustrating evaluation of an operating margin of a conventional semiconductor memory device. In the graph of FIG. 1A, a vertical axis denotes an external power voltage EVDD, a horizontal axis denotes an access time, “P” represents that it is determined as a normal operation by the function test, and “tRAS” represents an access time according to a specification.
As shown in FIG. 1A, the conventional semiconductor memory device operates while satisfying the access time according to the specification with a sufficient margin when the external power voltage is equal to or larger than 1.8 volts, whereas it operates without satisfying the access time according to the specification or without having a sufficient margin even though it satisfies the access time according to the specification when the external power voltage is equal to or less than 1.7 volts.
For example, the semiconductor memory device may normally operate at an external power voltage range of a high (low) level (equal to or larger than 1.8 volts), but does not operate normally at an external power voltage range of a low (high) level (equal to or less than 1.7 volts). To overcome the abnormal operation, the access time is varied by varying a control signal of the control signal setting portion to vary a delay time of the internal circuits, thereby adjusting the delay time so that the semiconductor memory device can operate at the external power voltage range of the high (low) level as well as the external power voltage range of the low (high) level.
However, even though the semiconductor memory device normally operates at the external power voltage range of the low (high) level by varying and setting the control signal of the control signal setting portion, the semiconductor memory device, which has operated normally at the external power voltage range of the high (low) level when the control signal is not set, may not operate normally at the external power voltage range of the high (low) level when the control signal is set.
FIG. 1B is a graph illustrating evaluation of an operating margin of a conventional semiconductor memory device when a control signal set by the control signal setting portion is applied. The semiconductor memory device satisfies the access time according to a specification with a sufficient margin when the external power voltage EVDD is equal to or less than 1.8 volts, whereas it does not satisfy the access time according to a specification when the external power voltage EVDD is equal to or larger than 1.9 volts.
As a result, the conventional semiconductor memory device may not operate normally at the external power voltage of a high level regardless of whether the control signal of the control signal setting portion is varied or not, making it difficult or impossible to relieve the abnormal semiconductor memory device.
Further, the semiconductor memory device does not operate normally since a range of the external power voltage may change, even during the normal operation of the semiconductor memory device. Thus, a conventional semiconductor memory device fails to satisfy a performance characteristic with a sufficient margin according to a specification.